COP8SAA5 datasheet(21/60 Pages) NSC

21 / 60 page

7.0 Timers (Continued)

the PMW outputs are useful in controlling motors, triacs, the

intensity of displays, and in providing inputs for data acquisi-

tion and sine wave generators.

In this mode, the timer T1 counts down at a fixed rate of t

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, R1A and R1B. The very

first underflow of the timer causes the timer to reload from

the register R1A. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the

timer for PWM mode operation.

Figure 15 shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the T1A output

pin. The underflows can also be programmed to generate in-

terrupts.

Underflows from the timer are alternately latched into two

pending flags, T1PNDA and T1PNDB. The user must reset

these pending flags under software control. Two control en-

able flags, T1ENA and T1ENB, allow the interrupts from the

timer underflow to be enabled or disabled. Setting the timer

enable flag T1ENA will cause an interrupt when a timer un-

derflow causes the R1A register to be reloaded into the

timer. Setting the timer enable flag T1ENB will cause an in-

terrupt when a timer underflow causes the R1B register to be

reloaded into the timer. Resetting the timer enable flags will

disable the associated interrupts.

Either or both of the timer underflow interrupts may be en-

abled. This gives the user the flexibility of interrupting once

per PWM period on either the rising or falling edge of the

PWM output. Alternatively, the user may choose to interrupt

on both edges of the PWM output.

7.2.2 Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, T1, is clocked by the input signal from the T1A pin. The

T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer

to be clocked either on a positive or negative edge from the

T1A pin. Underflows from the timer are latched into the

T1PNDA pending flag. Setting the T1ENA control flag will

cause an interrupt when the timer underflows.

In this mode the input pin T1B can be used as an indepen-

dent positive edge sensitive interrupt input if the T1ENB con-

trol flag is set. The occurrence of a positive edge on the T1B

input pin is latched into the T1PNDB flag.

Figure 16 shows a block diagram of the timer in External

Event Counter mode.

Note: The PWM output is not available in this mode since the T1A pin is be-

ing used as the counter input clock.

DS012838-22

FIGURE 15. Timer in PWM Mode

DS012838-23

FIGURE 16. Timer in External Event Counter Mode

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