MAC7101CVF datasheet(20/48 Pages) MOTOROLA

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MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Electrical Characteristics

3.9.1

Read and Write Bus Cycles

Table 23 lists processor bus output timings. Read/write bus timings listed in Table 23 are shown in Figure 7

and Figure 8.

Table 23. External Bus Output Timing Specifications

Num

Rating

Symbol

Min

Max

Unit

Control Outputs

L6a

CLKOUT high to chip selects valid 1

CSn transitions after the falling edge of CLKOUT.

tCHCV

—0.5tCYC + 10

L6b

CLKOUT high to byte select (BS[1:0]) valid 2

BSn transitions after the falling edge of CLKOUT.

tCHBV

—0.5tCYC + 10

L6c

CLKOUT high to output select (OE) valid 3

OE transitions after the falling edge of CLKOUT.

tCHOV

—0.5tCYC + 10

L7a

CLKOUT high to control output (BS[1:0], OE) invalid

tCHCOI 0.5tCYC + 2

—

L7b

CLKOUT high to chip selects invalid

tCHCI

0.5tCYC + 2

—

Address and Attribute Outputs

CLKOUT high to address (ADDR[21:0]) and control

(R/W) valid

tCHAV

—10

CLKOUT high to address (ADDR[21:0]) and control

(R/W) invalid

tCHAI

2—

Data Outputs

L10

CLKOUT high to data output (DATA[15:0]) valid

tCHDOV

—13

L11

CLKOUT high to data output (DATA[15:0]) invalid

tCHDOI

2—

L12

CLKOUT high to data output (DATA[15:0]) high impedance

tCHDOZ

—9

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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