®

7

PCM1721

DAC Section

System Clock Input

System Clock Input

for DAC Section

27MHz Master

Clock Input

PLL Generated

System Clock Out

Frequency

Selection ROM

Phase Detector

and Loop Filter

VCO

Sampling Frequency Selection

256f

N Counter

M Counter

4

1

2

TYPICAL CONNECTION DIAGRAM

Figure 1 illustrates the typical connection diagram for

PCM1721 in a MPEG2 application. The 27MHz master

programmable system clock is generated by the PCM1721

PLL, with SCKO used to drive the MPEG2 decoder’s

system clock input. The standard audio signals (data, bit

clock, and word clock) are generated in the decoder from

PCM1721’s system clock, providing synchonization of au-

dio and video signals.

PLL CIRCUIT

PCM1721 has a programmable internal PLL circuit, as

shown in Figure 2. The PLL is designed to accept a 27MHz

master clock and generate all internal system clocks required

to operate the digital filter and

∆Σ modulator, either at 256f

S

master clock’s frequency, and jitter on the system clock is

specified at 250ps maximum. Figure 3 illustrates the timing

requirements for the 27MHz master clock.

FIGURE 1. External Master Clock Input.

FIGURE 2. PPL Block Diagram.

FIGURE 3. MCKI, SCKI Input Timing.

t

CH

1/27MHz or

1/256f

t

CL

2.0V

0.8V

DIN

BCKIN

LRCIN

SCKO

SCKI

SERO

SCKO

LRCKO

SYSCKI

MCKIN

TEST

17

16

18

2

4

6

7

8

9

ML

MC

MD

RSTB

14

23

22

21

3

11

15

10

1

19

27MHz CLK OUT

+

10µF

Post

LPF

Post

LPF

Analog

Mute

Analog

Mute

STRB

SCKO

SDO

PIO

System

Controller

Rch Analog Out

Lch Analog Out

12

13

Audio

Decoder

256f

AGND

PGND DGND

V

CC

+5V Analog

+5V Analog

V

DD

V

CP

V

V

ZERO

CAP

PCM1721

Master

PLL

or

PCR

NOTE: (1) SCR: System Clock Reference

PCR: Program Clock Reference

200Ω