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EM78P447SAM 데이터시트(PDF) 21 Page - ELAN Microelectronics Corp |
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EM78P447SAM 데이터시트(HTML) 21 Page - ELAN Microelectronics Corp |
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21 / 55 page ![]() EM78P447S OTP ROM Wake-Up from Pin Change U U U U P U U P Bit Name /WUE7 /WUE6 /WUE5 /WUE4 /WUE3 /WUE2 /WUE1 /WUE0 0x0B IOCB Power-On 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-Up from Pin Change P P P P P P P P Bit Name X ODE WDTE SLPC ROC X X /WUE 0x0E IOCE Power-On U 0 1 1 0 U U 1 /RESET and WDT U 0 1 1 0 U U 1 Wake-Up from Pin Change U P 1 1 P U U P Bit Name X X X X EXIE X X TCIE 0x0F IOCF Power-On U U U U 0 U U 0 /RESET and WDT U U U U 0 U U 0 Wake-Up from Pin Change U U U U P U U P Bit Name - - - - - - - - 0x08 R8 Power-On 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-Up from Pin Change P P P P P P P P Bit Name - - - - - - - - 0x09~ 0x3E R9~R3E Power-On U U U U U U U U /RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P P ** To execute next instruction after the ”SLPC” bit status of IOCE register being on high-to-low transition. X: Not used. U: Unknown or don’t care. -: not defined. P: Previous value before reset. t: Check Table 6 2. The Status of RST, T, and P of STATUS Register A RESET condition is initiated by one of the following events: 1. A power-on condition, 2. A high-low-high pulse on /RESET pin, and 3. Watchdog timer time-out. The values of T and P (listed in Table 5 below) are used to verify the event that triggered the processor to wake up. Table 6 shows the events that may affect the status of T and P. Table 6 The Values of RST, T and P after RESET Reset Type T P Power on 1 1 /RESET during Operating mode *P *P /RESET wake-up during SLEEP1 mode 1 0 /RESET wake-up during SLEEP2 mode *P *P WDT during Operating mode 0 *P WDT wake-up during SLEEP1 mode 0 0 WDT wake-up during SLEEP2 mode 0 *P Wake-Up on pin change during SLEEP2 mode *P *P *P: Previous status before reset This specification is subject to change without prior notice. 06.25.2003 (V1.1) 21 |
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