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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADS5400HFS/EM 데이터시트(PDF) 6 Page - Texas Instruments |
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ADS5400HFS/EM 데이터시트(HTML) 6 Page - Texas Instruments |
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6 / 47 page  ADS5400-SP SLAS669D – SEPTEMBER 2010 – REVISED JANUARY 2014 www.ti.com SWITCHING CHARACTERISTICS Typical values at TA = 25°C, Min and Max values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT LVDS DIGITAL OUTPUTS (DATA, OVR/SYNCOUT, CLKOUT) VOD Differential output voltage (±) 247 350 454 mV Terminated 100 Ω differential VOC Common mode output voltage 1.125 1.25 1.375 V LVDS DIGITAL INPUTS (RESET) VID Differential input voltage (±) 175 350 mV Each input pin VIC Common mode input voltage 0.1 1.25 2.4 V RIN Input resistance 100 Ω CIN Input capacitance Each pin to ground 3.7 pF DIGITAL INPUTS (SCLK, SDIO, SDENB) VIH High level input voltage 2 AVDD3 + 0.3 V VIL Low level input voltage 0 0.8 V IIH High level input current ±1 μA IIL Low level input current ±1 μA CIN Input capacitance 2.9 pF DIGITAL INPUTS ( ENEXTREF, ENPWD, ENA1BUS) VIH High level input voltage 2 AVDD5 + 0.3 V VIL Low level input voltage 0 0.8 V IIH High level input current 125 μA ~40k Ω internal pull-down IIL Low level input current 20 μA CIN Input capacitance 2.9 pF DIGITAL OUTPUTS (SDIO, SDO) VOH High level output voltage IOH = 250 µA 2.8 V VOL Low level output voltage IOL = 250 µA 0.4 V CLOCK INPUTS RIN Differential input resistance CLKINP, CLKINN 100 130 190 Ω Input capacitance Estimated to ground from each CIN CLKIN pin, excluding soldered 4.8 pF packaged TIMING CHARACTERISTICS (1) Typical values at TA = 25°C, Min and Max values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT ta Aperture delay 250 ps Uncertainty of sample point due to internal jitter Aperture jitter, rms 125 fs sources Bus A, using Single Bus Mode 7 Bus A, using Dual Bus Mode Aligned 7.5 Latency Cycles Bus B, using Dual Bus Mode Aligned 8.5 Bus A and B, using Dual Bus Mode Staggered 7.5 (1) Timing parameters are specified by design or characterization, but not production tested. 6 Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: ADS5400-SP |
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