ADC08B200CIVSSLASHNOPB datasheet(4/39 Pages) TI1

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GND

50k

ADC08B200

SNAS388F – MARCH 2007 – REVISED APRIL 2013

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Pin No.

Symbol

Equivalent Circuit

Description

Output Edge Select or Test Mode Enable input. If this input is

high, the data outputs transition with the rising edge of the

OEDGE/TEN

DRDY output. If this input is low, the data outputs transition

with the falling edge of the DRDY output. Forcing a potential

of VA/2 at this input enables the Test Mode.

Synchronized WEN output. The WEN control input is

WENSYNC

synchronized on-chip with the internal sample clock and is

provided at this output.

Data Ready output. This signal transitions with the transition of

DRDY

the digital data outputs and indicates that the output data is

ready.

26 thru 29

and

D0–D7

Digital data digital Outputs. D0 is the LSB, D7 is the MSB.

33 thru 36

Buffer Full Flag. This output is high when the capture buffer is

full.

Buffer Empty Flag. This output is high when the capture buffer

is empty.

Auto-Stop Write input. This pin has a dual function. With the

buffer enabled, this pin acts as the ASW input. When this

input is high, writing to the buffer is halted when the capture

ASW

buffer is full (FF high). When the buffer is disabled, this pin is

ignored. When the device is in Test Mode, this pin acts as the

Output Edge Select signal, functioning in accordance with the

description of the OEDGE/TEN pin.

Buffer Size input. These inputs determine the size of the

23,24

BSIZE(1:0)

buffer, as described in the Functional Description.

Clock Multiply Factor input. These inputs determine the

38, 39

MULT(1:0)

internal clock PLL's multiplication factor.

Positive analog supply pin. Connect to a voltage source of

1, 4, 12

+3.3V.

43, 44, 48

PLL supply pin. Connect to a voltage source of +3.3V.

Digital core supply pin. Connect to a voltage source of +3.3V.

Power supply for the output drivers. Connect to a voltage

VDR

source of 2.7V to VD.

2, 5, 8, 11, 21,

GND

The ground return for the chip core.

42, 45, 47

SIG GND

Analog input signal ground.

DR GND

The ground return for the output drivers.

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