CC1021-RTR1 datasheet(27/91 Pages) TI1

27 / 91 page

307.2

ChBW

[kHz]

(DEC _ DIV

Not Recommended for New Designs NRND

CC1021

www.ti.com

SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

In Manchester mode the maximum modulating signal occurs when transmitting a continuous sequence of

0s (or 1s). In NRZ mode the maximum modulating signal occurs when transmitting a 0-1-0 sequence. In

both Manchester and NRZ mode 2 × fm is then equal to the programmed baud rate. The equation for SBW

can then be rewritten as shown in Equation 14.

SBW = Baud rate + frequency separation

(14)

Furthermore, the frequency offset of the transmitter and receiver must also be considered. Assuming

equal frequency error in the transmitter and receiver (same type of crystal) the total frequency error is

shown in Equation 15.

f_error = ±2 × XTAL_ppm × f_RF

(15)

Where:

XTAL_ppm is the total accuracy of the crystal including initial tolerance, temperature drift, loading and

ageing.

f_RF is the RF operating frequency.

The minimum receiver channel filter bandwidth (ChBW) can then be estimated as shown in Equation 16.

ChBW > SBW + 2 × f_error

(16)

The DEC_DIV[2:0] bits in the FILTER register control the receiver channel filter bandwidth. The 6 dB

bandwidth is given by Equation 17.

(17)

Where:

The IF frequency is set to 307.2 kHz.

Table 5-5 shows the available channel filter bandwidths.

There is a tradeoff between selectivity as well as sensitivity and accepted frequency tolerance. In

applications where larger frequency drift is expected, the filter bandwidth can be increased, but with

reduced adjacent channel rejection (ACR) and sensitivity.

Table 5-5. Channel Filter Bandwidth

FILTER BANDWIDTH

FILTER.DEC_DIV[2:0]

[kHz]

[decimal(binary)]

38.4

7 (111b)

43.9

6 (110b)

51.2

5 (101b)

61.4

4 (100b)

76.8

3 (011b)

102.4

2 (010b)

153.6

1 (001b)

307.2

0 (000b)

5.9.3

Demodulator, Bit Synchronizer and Data Decision

The block diagram for the demodulator, data slicer and bit synchronizer is shown in Figure 5-10. The built-

in bit synchronizer synchronizes the internal clock to the incoming data and performs data decoding. The

data decision is done using over-sampling and digital filtering of the incoming signal. This improves the

reliability of the data transmission. Using the synchronous modes simplifies the data-decoding task

substantially.

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC1021

CC1021-RTR1 데이터시트(PDF) 27 Page - Texas Instruments

CC1021-RTR1 데이터시트(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

데이터시트 다운로드

링크 URL