| 전자부품 데이터시트 검색엔진 |
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DP8344 데이터시트(PDF) 56 Page - National Semiconductor (TI) |
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DP8344 데이터시트(HTML) 56 Page - National Semiconductor (TI) |
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56 / 184 page ![]() 30 Transceiver (Continued) lates odd parity on the data byte (B2 – B9) and transmits this value for B10 If TCR 2 is high B10 takes the state of TCR 0 Odd Word Parity OWP controls the type of parity calculated on B1 – B11 and transmitted as B12 the frame delimiter If OWP is high odd parity is output other- wise even parity is transmitted In this manner the system designer is provided with maximum flexibility in defining the transmitted 3270 control bits (B10 – B12) When data is written to RTR the least significant 4 bits of TCR are loaded into the FIFO along with the data being written to RTR The same TCR contents can therefore be used for more than one frame of a multi-frame transmis- sion or changed for each frame When a 3270 frame is received and decoded the decoder loads the parallel data into the receive FIFO where it propa- gates through to the last location and is mapped into RTR and TSR Bits B2 – B11 are exactly as received Byte Pari- ty BP is odd parity on B2 – B9 calculated in the decoder Reading RTR will advance the receive FIFO therefore TSR must be read first if this information is to be utilized TLF9336 – 47 (a) 3270 Data and Command Frames TLF9336 – 48 (b) 3299 Address Frame FIGURE 3-9 32703299 Frame AssemblyDisassembly Procedure 56 |
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