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DAC7573 I

Address Byte

DAC7573

SLAS398 – SEPTEMBER 2003

The DAC7573 requires a start condition, a valid I

single update. After the receipt of each byte, DAC7573 acknowledges by pulling the SDA line low during the high

period of a single clock pulse. A valid I

mode of the selected DAC7573. Once the operational mode is selected by the control byte, DAC7573 expects an

MSB byte followed by an LSB byte for data update to occur. DAC7573 performs an update on the falling edge of

the acknowledge signal that follows the LSB byte.

The control byte needs not to be resent until a change in operational mode is required. The bits of the control

byte continuously determine the type of update performed. Thus, for the first update, DAC7573 requires a start

condition, a valid I

DAC7573 needs an MSB byte, and an LSB byte as long as the control command remains the same.

Using the I

the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge

rate is limited to 22.22 KSPS. Once a stop condition is received, DAC7573 releases the I

new start condition.

MSB

LSB

1

0

0

1

1

A1

A0

R/W

The address byte is the first byte received following the START condition from the master device. The first five

bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select

TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of

the DAC7573. Up to 16 devices (DAC7573) can still be connected to the same I

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