CD74ACT175

QUADRUPLE D-TYPE FLIP-FLOP

WITH CLEAR

SCHS345 – APRIL 2003

1

POST OFFICE BOX 655303

Outputs

Significantly Reduced Power Consumption

– Fanout to 15 F Devices

Circuit Design

MIL-STD-883, Method 3015

– Buffer/Storage Registers

– Shift Registers

– Pattern Generators

description/ordering information

This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features

complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not

directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low

level, the D input has no effect at the output.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – E

Tube

CD74ACT175E

CD74ACT175E

–55

°C to 125°C

SOIC

M

Tube

CD74ACT175M

ACT175M

SOIC – M

Tape and reel

CD74ACT175M96

ACT175M

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

CLR

CLK

D

Q

Q

L

X

X

L

H

H

↑

HH

L

H

↑

LL

H

H

L

X

Q0

Q0

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

E OR M PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CLR

1Q

1Q

1D

2D

2Q

2Q

GND

4Q

4Q

4D

3D

3Q

3Q

CLK

Copyright

 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.