DP83846AVHG datasheet(39/59 Pages) NSC

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This counter provides information required to implement the “FalseCarriers” attribute within the MAU managed object

class of Clause 30 of the IEEE 802.3u speciﬁcation.

This counter provides information required to implement the “SymbolErrorDuringCarrier” attribute within the PHY man-

aged object class of Clause 30 of the IEEE 802.3u speciﬁcation.

Table 17. False Carrier Sense Counter Register (FCSCR), address 0x14

Bit

Bit Name

Default

Description

15:8

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

7:0

FCSCNT[7:0]

0, RW / COR

False Carrier Event Counter:

This 8-bit counter increments on every false carrier event. This

counter sticks when it reaches its max count (FFh).

Table 18. Receiver Error Counter Register (RECR), address 0x15

Bit

Bit Name

Default

Description

15:8

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

7:0

RXERCNT[7:0]

0, RW / COR

RX_ER Counter:

This 8-bit counter increments for each receive error detected.

When a valid carrier is present and there is at least one occurrence

of an invalid data symbol. This event can increment only once per

valid carrier event. If a collision is present, the attribute will not in-

crement. The counter sticks when it reaches its max count.

Table 19. 100 Mb/s PCS Conﬁguration and Status Register (PCSR), address 0x16

Bit

Bit Name

Default

Description

15:13

RESERVED

<00>, RO

RESERVED: Writes ignored, Read as 0.

BYP_4B5B

0, RW

Bypass 4B/5B Encoding:

1 = 4B5B encoder functions bypassed.

0 = Normal 4B5B operation.

FREE_CLK

0, RW

Receive Clock:

1 = RX_CK is free-running.

0 = RX_CK phase adjusted based on alignment.

TQ_EN

0, RW

100Mbs True Quiet Mode Enable:

1 = Transmit True Quiet Mode.

0 = Normal Transmit Mode.

SD FORCE PMA

0,RW

Signal Detect Force PMA:

1 = Forces Signal Detection in PMA.

0 = Normal SD operation.

SD_OPTION

1, RW

Signal Detect Option:

1 = Enhanced signal detect algorithm.

0 = Reduced signal detect algorithm.

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