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DP83847 데이터시트(PDF) 9 Page - National Semiconductor (TI)

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부품명 DP83847
상세설명  DsPHYTER II ??Single 10/100 Ethernet Transceiver
PDF  60 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83847 데이터시트(HTML) 9 Page - National Semiconductor (TI)

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1.7 Reset
1.8 Power and Ground Pin
RX_ER/PAUSE_EN
S, O, PU
33
PAUSE ENABLE: This strapping option allows advertisement of
whether or not the DTE(MAC) has implemented both the optional
MAC control sublayer and the pause function as specified in
clause 31 and annex 31B of the IEEE 802.3x specification (Full
Duplex Flow Control).
When left floating the Auto-Negotiation Advertisement Register
will be set to 0, indicating that Full Duplex Flow Control is not sup-
ported.
When tied low through a 5 k
Ω, the Auto-Negotiation Advertise-
ment Register will be set to 1, indicating that Full Duplex Flow
Control is supported.
The float/pull-down status of this pin is latched into the Auto-Ne-
gotiation Advertisement Register during Hardware-Reset.
CRS/LED_CFG
S, O,
PU
45
LED CONFIGURATION: This strapping option defines the polar-
ity and function of the FDPLX LED pin.
See Section 2.3 for further descriptions of this strapping option.
Signal Name
Type
LLP Pin #
Description
Signal Name
Type
LLP Pin #
Description
RESET
I46
RESET: Active Low input that initializes or re-initializes the
DP83847. Asserting this pin low for at least 160
µs will force a re-
set process to occur which will result in all internal registers re-ini-
tializing to their default states as specified for each bit in the
Register Block section and all strapping options are re-initialized.
Signal Name
LLP Pin #
Description
TTL/CMOS INPUT/OUTPUT SUPPLY
IO_VDD
28, 56
I/O Supply
IO_GND
GND
I/O Ground
INTERNAL SUPPLY PAIRS
CORE_VDD
Internal
Digital Core Supply
CORE_GND
GND
Digital Core Ground
ANALOG SUPPLY PINS
ANA_VDD
14
Analog Supply
ANA_GND
GND
Analog Ground
SUBSTRATE GROUND
SUB_GND
GND
Bandgap Substrate connection



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