BQ28Z560DRZR-R1 datasheet(2/61 Pages) TI1

2 / 61 page

bq28z560-R1

SLUSBD3 – APRIL 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION(1)

PART NUMBER

PACKAGE

TAPE AND REEL QUANTITY

bq28z560-R1DRZR

3000

12-pin, 2.5-mm × 4.0-mm

–40°C to 85°C

SON

bq28z560-R1DRZT

250

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder on ti.com (www.ti.com).

THERMAL INFORMATION

bq28z560-R1

THERMAL METRIC(1)

SON

UNITS

12 PINS

θJA

Junction-to-ambient thermal resistance(2)

186.4

θJC(top)

Junction-to-case(top) thermal resistance (3)

90.4

θJB

Junction-to-board thermal resistance (4)

110.7

°C/W

ψJT

Junction-to-top characterization parameter (5)

96.7

ψJB

Junction-to-board characterization parameter (6)

θJC(bottom)

Junction-to-case(bottom) thermal resistance (7)

n/a

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-board characterization parameter,

ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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