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DP83905AVQB 데이터시트(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 DP83905AVQB
상세설명  AT Local Area Network Twisted-Pair Interface Controller
PDF  80 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83905AVQB 데이터시트(HTML) 2 Page - National Semiconductor (TI)

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General Description (Continued)
The integrated ENDEC module allows Manchester encod-
ing and decoding via a differential transceiver and phase
lock Ioop decoder at 10 Mbitsec Also included are a colli-
sion detect translator and diagnostic loopback capability
The ENDEC module interfaces directly to the transceiver
module and also provides a fully IEEE compliant AUI (At-
tachment Unit Interface) for connection to other media
transceivers
The Media Access Control function which is provided by the
Network Interface Control module (NIC) provides simple
and efficient packet transmission and reception control by
means of off-board memory which can be accessed either
through an IO port or mapped into the system memory
ATLANTIC Controller provides a comprehensive solution
for 10BASE-T IEEE 8023 networks Due to the inherent
constraints of CMOS processing isolation is required at the
AUI differential signal interface for 10BASE5 and 10BASE2
applications
Table of Contents
10 SYSTEM DIAGRAM
11 Connection Diagram
20 PIN DESCRIPTION
30 SIMPLIFIED APPLICATION DIAGRAM
40 FUNCTIONAL DESCRIPTION
41 Bus Interface Block
42 Power on RESET operation
43 EEPROM Operation
44 Jumpered and Jumperless Operation Support
45 Low Power Operation
46 Boot PROM Operation
47 DP8390 Core (Network Interface Controller)
48 Twisted Pair Interface Module
49 EncoderDecoder (ENDEC) Module
50 REGISTER DESCRIPTIONS
51 Configuration Registers
52 Shared Memory Mode Control Registers
53 NIC Core Registers
54 DP8390 Core DMA Registers
60 OPERATION OF ATLANTIC CONTROLLER
61 TransmitReceive Packet Encapsulation
Decapsulation
62 Buffer Memory Access Control (DMA)
63 Packet Reception
64 Packet Transmission
65 Loopback Diagnostics
66 Memory Arbitration and Bus Operation
67 Functional Bus Timing
70 PRELIMINARY ELECTRICAL CHARACTERISTICS
80 PRELIMINARY SWITCHING CHARACTERISTICS
90 AC TIMING TEST CONDITIONS
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