ADP3421 datasheet(3/12 Pages) AD

3 / 12 page

REV. A

–3–

ADP3421

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

CURRENT LIMIT COMPARATOR

Input Offset Voltage

VCLOS

VCS– = 1.3 V

–6

Input Bias Current

ICL+

VCS+ = 1.3 V

–5

µA

Hysteresis Current

ICL–

VCORE = VRAMP = 1.3 V

VREG = 1.28 V, VCS– = 1.3 V

VCS+ = 1.28 V

RIHYS Open

–5

µA

RIHYS = 170 k

Ω

–22

–30

–38

µA

RIHYS = 17 k

Ω

–265

–300

–335

µA

VCS+ = 1.32 V

RIHYS Open

–5

µA

RIHYS = 170 k

Ω

–13

–20

–27

µA

RIHYS = 17 k

Ω

–175

–200

–225

µA

Hysteresis Setting Reference Voltage VVHYS

1.53

1.70

1.87

Propagation Delay Time

tCLPD

TA = 25

°C30

°C ≤ TA ≤ 100°C

100

LINEAR REGULATOR SOFT-START TIMER

Charge Current

ISSC(UP)

VSSC = 0 V

–0.6

–1.0

–1.4

µA

Discharge Current

ISSC(DN)

VSSC = 1.7 V, VUVLO = 1.1 V

0.3

1.0

Enable Threshold

VSSCEN

150

400

Termination Threshold

VSSCTH

1.53

1.70

1.87

2.5 V CLK LDO CONTROLLER

Feedback Bias Current

ICLKFB

VCLKFB = 2.5 V

12.5

µA

Output Drive Current

ICLKDRV

VCLKDRV = 2.55 V

µA

VCLKDRV = 2.45 V

DC Transconductance

GCLK

∆I

CLKDRV = 1 mA

500

mA/V

1.5 V I/O LDO CONTROLLER

Feedback Bias Current

IIOFB

VIOFB = 1.5 V

7.5

µA

Output Drive Current

IIODRV

VIODRV = 1.53 V

µA

VIODRV = 1.47 V

DC Transconductance

GIO

∆I

CLKDRV = 1 mA

650

mA/V

LEVEL TRANSLATOR

Input Clamping Threshold

VLTIH

ILTI = –10

µA

0.95

1.5

Output Voltage

VLTOH

ILTI = –10

µA9

0.9

× VCCLT

VCCLT

VLTOL

VLTI = 0.175 V

375

Propagation Delay Time

tLTPD

NOTES

CORE ramps up monotonically.

CORE ramps down monotonically.

3During latency time of VID code change, the Power Good output signal should not be considered valid.

4Internal bias and soft start are not enabled unless the soft-start pin voltage ﬁrst drops below the enable threshold.

5Measured from 50% of VID code transient amplitude to the point where V

DAC settles within

±1% of its steady state value.

6Guaranteed by characterization.

740 mV p-p amplitude impulse with 20 mV overdrive. Measure from the input threshold intercept point to 50% of the output voltage swing.

8Measured between the 30% and 70% points of the output voltage swing.

9The LTO output tied to V

CCLT = 2.5 V rail through an RLTO = 150

Ω pull-up resistor.

Speciﬁcations subject to change without notice.

ADP3421 데이터시트(PDF) 3 Page - Analog Devices

ADP3421 데이터시트(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

데이터시트 다운로드

링크 URL