LM1972

SNAS094D – APRIL 1995 – REVISED MARCH 2013

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Timing Diagram

Figure 3. Timing Diagram

PIN DESCRIPTIONS

Signal Ground (3, 19): Each input has its own independent ground, GND1 and GND2.

Signal Input (4, 20): There are 2 independent signal inputs, IN1 and IN2.

Signal Output (2, 17): There are 2 independent signal outputs, OUT1 and OUT2.

configuration.

AC Ground (1, 5, 6, 14, 16): These five pins are not physically connected to the die in any way (i.e., No

bondwires). These pins must be AC grounded to prevent signal coupling between any of the pins nearby.

Pin 14 should be connected to pins 13 and 15 for ease of wiring and the best isolation, as an example.

Logic Ground (8): Digital signal ground for the interface lines; CLOCK, LOAD/SHIFT, DATA-IN and DATA-OUT.

Clock (9): The clock input accepts a TTL or CMOS level signal. The clock input is used to load data into the

internal shift register on the rising edge of the input clock waveform.

Load/Shift (10): The load/shift input accepts a TTL or CMOS level signal. This is the enable pin of the device,

allowing data to be clocked in while this input is low (0V).

Data-In (11): The data-in input accepts a TTL or CMOS level signal. This pin is used to accept serial data from

a microcontroller that will be latched and decoded to change a channel's attenuation level.

Data-Out (12): This pin is used in daisy-chain mode where more than one

μPot is controlled via the same data

line. As the data is clocked into the chain from the

μC, the preceding data in the shift register is shifted out

the DATA-OUT pin to the next

μPot in the chain or to ground if it is the last μPot in the chain. The

LOAD/SHIFT line goes high once all of the new data has been shifted into each of its respective registers.

4

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