AN983 datasheet(30/91 Pages) ETC

30 / 91 page

AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

6 ~ 2

DSL

Descriptor Skip Length. Defines the gap between two

descriptions in the units of DW.

R/W*

BAR

Bus arbitration

0: receive higher priority

1: transmit higher priority

R/W*

SWR

Software reset

1: reset all internal hardware, except configuration

registers. This signal will be cleared by AN983B itself after it

completed the reset process.

R/W*

R/W* = before writing the transmit and receive operations should be stopped.

CSR1 (offset = 08h), TDR - Transmit demand register

Bit #

Name

Descriptions

Default Val RW Type

31~ 0

TPDM

Transmit poll demand

When written any value in suspended state, trigger

read-tx-descriptor process and check the own-bit, if

own-bit = 1, then start transmit process

ffffffffh

R/W*

R/W* = before writing the transmit process should be in the suspended state.

CSR2 (offset = 10h), RDR - Receive demand register

Bit #

Name

Descriptions

Default Val RW Type

31 ~ 0

RPDM

Receive poll demand

When written any value in suspended state, trigger the

read-rx-descriptor process and check own-bit, if own-

bit =

1, then start move data to buffer from FIFO

ffffffffh

R/W*

R/W* = before writing the receive process should be in the suspended state.

CSR3 (offset = 18h), RDB - Receive descriptor base address

Bit #

Name

Descriptions

Default Val RW Type

31~ 2

SAR

Start address of receive descriptor

xxxxxxx

R/W*

1, 0

RBND

Must be 00, DW boundary

R/W* = before writing the receive process should be stopped.

CSR4 (offset = 20h), TDB - Transmit descriptor base address

Bit #

Name

Descriptions

Default Val RW Type

31~ 2

SAT

Start address of transmit descriptor

xxxxxx

R/W*

1, 0

TBND

Must be 00, DW boundary

R/W* = before writing the transmit process should be stopped.

CSR5 (offset = 28h), SR - Status register

Bit #

Name

Descriptions

Default Val RW Type

31~ 26

----

Reserved

25~ 23

BET

Bus Error Type. This field is valid only when bit 13 of CSR5

(fatal bus error) is set. There is no interrupt generated by

this field.

000

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

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