®

AS7C256A

9/24/04; v.1.2

Alliance Semiconductor

P. 2 of 9

Functional description

The AS7C256A is a 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized

as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including

operation without sacrificing performance or operating margins.

≤11 mW. Normal operation offers 75%

power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.

memory organizations.

A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7

is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should

drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write

enable is low, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 ±0.5V supply. The AS7C256A is packaged

in high volume industry standard packages.

Absolute maximum ratings

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Truth table

Parameter

Symbol

Min

Max

Unit

–0.5

+7.0

V

Voltage on any pin relative to GND

–0.5

V

Power dissipation

–1.0

W

Storage temperature (plastic)

–65

+150

–55

+125

DC current into outputs (low)

–20

mA

CE

WE

OE

Data

Mode

H

X

X

High Z

L

H

H

High Z

LHL

LL

X