WM8750 datasheet(38/60 Pages) WOLFSON

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WM8750BL

Production Data

PD, Rev 4.1, August 2012

Note: For optimum ADC audio performance in slave mode, the BCLK input signal should be

configured to transition at the same time as the falling edge of MCLK.

The ADCDAT digital data output is buffered inside the CODEC using a digital logic buffering block.

However, the ADCDAT buffering block is not reset by the power-on reset circuit and hence the

ADCDAT pin stage (logic high or logic low) is undefined at power up until data is clocked out from the

ADC. Implementation of either of these workarounds will ensure correct operation:



Ensure that any external connection to the ADCDAT pin is made with the understanding

that ADCDAT pin may be driven high or low by the CODEC until ADC data is clocked out.



Tri-state the ADCDACDAT output pin by setting the TRI bit in R24 (Additional Control 2

the CODEC has no internal pull-up/down resistors) the input voltage level must be set on

these pins by an external source (either the device connected to the digital audio interface

or pull-up/down resistors) to prevent excess current consumption.

AUDIO DATA FORMATS

In I

2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

Figure 18 I

2S Audio Interface Format (assuming n-bit word length)

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 19 Left Justified Audio Interface (assuming n-bit word length)

WM8750 데이터시트(PDF) 38 Page - Wolfson Microelectronics plc