LM3560TLXSLASHNOPB datasheet(28/48 Pages) TI1

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R/W

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 7

Bit 6

MSB

LSB

C Slave Address (chip address)

tRISE

tFALL

70%

30%

70%

30%

tFALL

70%

30%

tRISE

70%

30%

tHD;STA

1/fSCL

tHD;DAT

tSU;DAT

tHIGH

tLOW

tVD;DAT

70%

30%

th Clock

Pulse

Start

Stop

tSU;STA

tHD;STA

tVD;ACK

th Clock

Pulse

70%

30%

tSU;STO

tBUF

Start

Repeated

Start

70%

30%

70%

30%

70%

30%

70%

SCL

SDA

(Continued)

SCL

(Continued)

30%

LM3560

SNOSB43B – SEPTEMBER 2011 – REVISED AUGUST 2013

www.ti.com

Figure 42. I2C-Compatible Timing

I2C-COMPATIBLE CHIP ADDRESS

The device address for the LM3560 is 1010011 (0xA7 for read and 0xA6 for write). After the START condition,

the I2C master sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE

and R/W = 1 indicates a READ. The second byte following the device address selects the register address to

which the data will be written. The third byte contains the data for the selected register.

Figure 43. Device Address

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