DP8464B datasheet(20/26 Pages) NSC

20 / 26 page

Application Information (Continued)

Another troublesome input pattern which should be investi-

gated is a high frequency triplet surrounded by the lowest

frequency as shown in

Figure 20 Since the center bit of the

triplet does not rise very much above the baseline there is

the possibility it will not trip the hysteresis level This pattern

should be checked to ensure the gating channel filter raises

this center bit enough for the proper operation of the gating

channel The operation of the triplet in the previous example

is shown in

Figure 21

LAYOUT CONSIDERATIONS

Figure 22 is a top view of the component layout for the

DP8464B application board whose schematic is shown in

Figure 23 Care must be exercised in the board layout in

order to isolate all digital signals from analog signals The

layout shown in

Figure 22 is a good example of what is

required in this regard In particular the Amp In pins (pins 6

and 7) and the CDIFF pins (pins 1 and 24) must be isolated

from all digital signals An analog ground plane will greatly

aid in this isolation as will separate digital and analog

grounds The VCC (pin 9) should have a 01 mf bypass ca-

pacitor to analog ground located close to the DP8464B The

component list is provided as an example These compo-

nents will need to be optimized for a specific read channel

TLF5283 – 26

FIGURE 20 (27) Triplet

TLF5283 – 27

FIGURE 21 Region 2 Triplet Operation

DP8464B 데이터시트(PDF) 20 Page - National Semiconductor (TI)