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LM5134

SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

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10 Layout

10.1 Layout Guidelines

Attention must be given to board layout when using LM5134. Some important considerations include:

1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and

discharge the FETs gate into a minimal physical area. This will decrease the loop inductance and minimize

noise issues on the gate.

2. To reduce the loop inductance, the driver should be placed as close as possible to the FETs. The gate trace

to and from the FETs are recommended to be placed closely side by side, or directly on top of one another.

3. The parasitic source inductance, along with the gate capacitor and the driver pulldown path, can form a LCR

resonant tank, resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to damp

the ringing.

10.2 Layout Example

Figure 27. LM5134 Layout Example