SC28L91 datasheet(12/42 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22

AC CHARACTERISTICS (5 VOLT) 1, 2, 3, 4

VCC = 5.0V ± 10%, Tamb = –40°C to +85°C, unless otherwise specified.

Symbol

Parameter

Min

Typ

Max

Unit

Reset Timing (See Figure 4)

tRES

Reset pulse width

100

Bus Timing5 (See Figure 5)

t*AS

A0–A3 setup time to RDN, WRN Low

t*AH

A0–A3 hold time from RDN, WRN low

t*CS

CEN setup time to RDN, WRN low

t*CH

CEN Hold time from RDN. WRN low

t*RW

WRN, RDN pulse width (Low time)

t*DD

Data valid after RDN low (125pF load. See Figure 3 for smaller loads.)

t*DA

RDN low to data bus active6

t*DF

Data bus floating after RDN or CEN high

t*DI

RDN or CEN high to data bus invalid7

t*DS

Data bus setup time before WRN or CEN high (write cycle)

t*DH

Data hold time after WRN high

–12

t*RWD

High time between read and/or write cycles5, 7

Port Timing5 (See Figure 9)

t*PS

Port in setup time before RDN low (Read IP ports cycle)

–20

t*PH

Port in hold time after RDN high

–20

t*PD

OP port valid after WRN or CEN high (OPR write cycle)

Interrupt Timing (See Figure 10)

t*IR

INTRN (or OP3–OP7 when used as interrupts) negated from:

Read RxFIFO (RxRDY/FFULL interrupt)

Write TxFIFO (TxRDY interrupt)

Reset Command (delta break change interrupt)

Stop C/T command (Counter/timer interrupt

Read IPCR (delta input port change interrupt)

Write IMR (Clear of change interrupt mask bit(s))

Clock Timing (See Figure 11)

t*CLK

X1/CLK high or low time

f*CLK

X1/CLK frequency8 (for higher speeds contact factory)

0.1

3.686

8.0

MHz

f*CTC

C/T Clk (IP2) high or low time (C/T external clock input)

f*CTC

C/T Clk (IP2) frequency8 (for higher speeds contact factory)

8.0

MHz

t*RX

RxC high or low time (16X)

f*RX

RxC Frequency (16X)(for higher speeds contact factory)

MHz

RxC Frequency (1x)8, 9

MHz

t*TX

TxC High or low time (16X)

f*TX

TxC frequency (16X) (for higher speeds contact factory)

MHz

TxC frequency (1X)8, 9

MHz

Transmitter Timing, external clock (See Figure 12)

t*TXD

TxD output delay from TxC low (TxC input pin)

t*TCS

Output delay from TxC output pin low to TxD data output

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