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LM8328TMX/NOPB 데이터시트(PDF) 37 Page - Texas Instruments

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부품명 LM8328TMX/NOPB
상세설명  LM8328 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface
PDF  56 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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LM8328TMX/NOPB 데이터시트(HTML) 37 Page - Texas Instruments

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LM8328
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SNLS328A – AUGUST 2011 – REVISED MARCH 2013
GPIOIS1 - Interrupt Sense Configuration Register 1
Table 67. GPIOIS1 - Interrupt Sense Configuration Register 1
Register - Name
Address
Type
Register Function
GPIOIS1
0xCA
R/W
Interrupt type on KPY[7:0]
Bit - Name
Bit
Default
Bit Function
Interrupt type bits for KPY[7:0]
KPY[7:0]IS
7:0
0x0
0: edge sensitive interrupt
1: level sensitive interrupt
GPIOIS2 - Interrupt Sense Configuration Register 2
Table 68. GPIOIS2 - Interrupt Sense Configuration Register 2
Register - Name
Address
Type
Register Function
GPIOIS2
0xCB
R/W
Interrupt type on KPY[11:8]
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
(reserved)
Interrupt type bits for KPY[11:8]
KPY[11:8]IS
3:0
0x0
0: edge sensitive interrupt
1: level sensitive interrupt
GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0
Table 69. GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0
Register - Name
Address
Type
Register Function
Defines whether an interrupt on KPX[7:0] is triggered on both edges or on
GPIOIBE0
0xCC
R/W
a single edge. See Table 72 for the edge configuration.
Bit - Name
Bit
Default
Bit Function
Interrupt both edges bits for KPX[7:0]
KPX[7:0]IBE
7:0
0x0
0: interrupt generated at the active edge
1: interrupt generated after both edges
GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1
Table 70. GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1
Register - Name
Address
Type
Register Function
Defines whether an interrupt on KPY[7:0] is triggered on both edges or on
GPIOIBE1
0xCD
R/W
a single edge. See Table 73 for the edge configuration.
Bit - Name
Bit
Default
Bit Function
Interrupt both edges bits for KPY[7:0]
KPY[7:0]IBE
7:0
0x0
0: interrupt generated at the configured edge
1: interrupt generated after both edges
GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2
Table 71. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2
Register - Name
Address
Type
Register Function
Defines whether an interrupt on KPY[11:8] is triggered on both edges or
GPIOIBE2
0xCE
R/W
on a single edge. See Table 74 for the edge configuration.
Bit - Name
Bit
Default
Bit Function
Copyright © 2011–2013, Texas Instruments Incorporated
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