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2015-07-0033

PT0523-4

8/18/15

7

PI4MSD5V9542A

2 Channel I2C bus Multiplexer

with Interrupt Logic

Device addressing

Following a START condition the bus master must output the address of the slave it is accessing. The address of

the PI4MSD5V9542A is shown in Figure 4.

To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they

must be pulled HIGH or LOW.

The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while

a logic 0 selects a write operation.

Figure 4:Device address

Control register

Following the successful acknowledgement of the slave address, the bus master will send a byte to the

PI4MSD5V9542A which will be stored in the control register. If multiple bytes are received by the PI4MSD5V9542A,

it will save the last byte received. This register can be written and read via the I2C-bus.

Figure 5: Control register

Control register definition

A SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written

after the PI4MSD5V9542A has been addressed. The 3 LSBs of the control byte are used to determine which channel is

to be selected. When a channel is selected, it will become active after a STOP condition has been placed on the I2C-

bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false

conditions are generated at the time of connection.

Bits INT0/, INT1/, D6 and D7 are all writable, but will read the chip status. INT0/ and INT1/ indicate the state of

the corresponding interrupt input. D7 and D6 always read 0.

D7

D6

INT1

INT0

D3

B2

B1

B0

Command

X

X

X

X

X

0

X

X

no channel selected

X

X

X

X

X

1

0

0

channel 0 enabled

X

X

X

X

X

1

0

1

channel 1 enabled

X

X

X

X

X

1

1

X

no channel selected

0

0

0

0

0

0

0

0

no channel selected;

power-up default state

Control register: Write—channel selection; Read—channel status.