SN761677

SLES066A – DECEMBER 2002

www.ti.com

3

ELECTRICAL CHARACTERISTICS

VCC = 4.5 V to 5.5 V, TA = –20°C to 85°C (unless otherwise noted)(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Total Device and Serial Interface

ICC1

Supply current 1 (VCC)

75

95

mA

ICC2

Supply current 2 (VCC)

One band switch on (IBS = 10 mA)

85

105

mA

ICC3

Supply current 3 (TUVCC)

IVDC = 50 µA

4

10

mA

VIH

High-level input voltage (SCL, SDA)

3

V

VIL

Low-level input voltage (SCL, SDA)

1.5

V

IIH

High-level input current (SCL, SDA)

10

µA

IIL

Low-level input current (SCL, SDA)

–10

µA

VPOR

Power-on reset supply voltage

Threshold of supply voltage between reset

and operation mode

2.1

3.7

4

V

DC/DC Converter

VO(VDC)

Output voltage (VDC)

IVDC = 50 µA

35

V

IC(VDCM)

Output current (VDC)

230

µA

ts

Output settling time (VDC)

From VTUVCC > 4.5 V to VO(VDC) < 28 V

100

ms

I2C Interface

VASH

Address select high-input voltage (AS)

VCC = 5 V

4.5

5

V

VASM

Address select mid-input voltage (AS)

VCC = 5 V

2

3

V

VASL

Address select low-input voltage (AS)

VCC = 5 V

0.5

V

IASH

Address select high-input current (AS)

10

µA

IASL

Address select low-input current (AS)

–10

µA

VI(ADC)

ADC input voltage

See Table 9

0

VCC

V

IIH(ADH)

ADC high-level input current

VI(ADC) = VCC

10

µA

IIL(ADL)

ADC low-level input current

VI(ADC) = 0 V

–10

µA

VOL

Low-level output voltage (SDA)

VCC = 5 V, IOL = 3 mA

0.4

V

llkg(SDA)

High-level output leakage current

(SDA)

VSDA = 5.5 V

10

µA

FSCL

Clock frequency (SCL)

100

400

kHz

th(DAT)

Data hold time

See timing chart in Figure 1

0

µs

tBUF

Bus free time

1.3

µs

th(STA)

Start hold time

0.6

µs

th(low)

SCL low hold time

0.6

µs

th(lhigh)

SCL high hold time

0.6

µs

tsu(STA)

Start setup time

0.6

µs

tsu(DAT)

Data setup time

0.1

µs

tr

SCL, SDA rise time

0.3

µs

tf

SCL, SDA fall time

0.3

µs

tsu(STO)

STOP setup time

0.6

µs