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TAS5709APHPR 데이터시트(PDF) 10 Page - Texas Instruments

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부품명 TAS5709APHPR
상세설명  20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC
PDF  61 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

TAS5709APHPR 데이터시트(HTML) 10 Page - Texas Instruments

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AC Characteristics (BTL)
SERIAL AUDIO-PORT SLAVE MODE
TAS5709, TAS5709A
SLOS599A – NOVEMBER 2008 – REVISED SEPTEMBER 2009 ..................................................................................................................................... www.ti.com
PVDD_X = 18 V, BTL AD mode, FS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter,
fPWM = 384 kHz, TA = 25°C (unless otherwise noted). All performance is in accordance with recommended operating
conditions, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PVDD = 18 V, 10% THD, 1-kHz input
20.6
signal
PVDD = 18 V, 7% THD, 1-kHz input signal
19.5
PVDD = 12 V, 10% THD, 1-kHz input
9.4
PO
Power output per channel
W
signal
PVDD = 12 V, 7% THD, 1-kHz input signal
8.9
PVDD = 8 V, 10% THD, 1-kHz input signal
4.1
PVDD = 8 V, 7% THD, 1-kHz input signal
3.8
PVDD = 18 V; PO = 1 W
0.06%
THD+N
Total harmonic distortion + noise
PVDD = 12 V; PO = 1 W
0.13%
PVDD = 8 V; PO = 1 W
0.2%
Vn
Output integrated noise (rms)
A-weighted
56
µV
PO = 0.25 W, f = 1kHz (BD Mode)
–82
dB
Crosstalk
PO = 0.25 W, f = 1kHz (AD Mode)
–69
dB
A-weighted, f = 1 kHz, maximum power at
SNR
Signal-to-noise ratio (1)
106
dB
THD < 1%
(1)
SNR is calculated relative to 0-dBFS input level.
over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
CL = 30 pF
1.024
12.288
MHz
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
ns
LRCLK frequency
8
48
48
kHz
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
SCLK
SCLK rising edges between LRCLK rising edges
32
64
edges
t(edge)
SCLK
LRCLK clock edge with respect to the falling edge of SCLK
–1/4
1/4
period
tr /
ns
Rise/fall time for SCLK/LRCLK
8
tf(SCLK/LRCLK)
10
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Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5709 TAS5709A



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