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THS1041CPWR 데이터시트(PDF) 6 Page - Texas Instruments

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부품명 THS1041CPWR
상세설명  10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP
PDF  42 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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THS1041CPWR 데이터시트(HTML) 6 Page - Texas Instruments

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THS1041
SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004
6
www.ti.com
electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 Vpp and 2 Vpp, PGA = 1X, TA = Tmin to Tmax (unless otherwise noted) (continued)
dynamic performance (ADC and PGA)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENOB
Effective number of bits
f = 4.8 MHz, −0.5 dBFS
8.8
9.6
Bits
ENOB
Effective number of bits
f = 20 MHz, −0.5 dBFS
9.5
Bits
SFDR
Spurious free dynamic range
f = 4.8 MHz, −0.5 dBFS
60.5
72
dB
SFDR
Spurious free dynamic range
f = 20 MHz, −0.5 dBFS
70
dB
THD
Total harmonic distortion
f = 4.8 MHz, −0.5 dBFS
− 72.5
− 61.3
dB
THD
Total harmonic distortion
f = 20 MHz, −0.5 dBFS
− 71.6
dB
SNR
Signal-to-noise ratio
f = 4.8 MHz, −0.5 dBFS
55.7
60
dB
SNR
Signal-to-noise ratio
f = 20 MHz, −0.5 dBFS
57
dB
SINAD
Signal-to-noise and distortion
f = 4.8 MHz, −0.5 dBFS
55.6
59.7
dB
SINAD
Signal-to-noise and distortion
f = 20 MHz, −0.5 dBFS
59.6
dB
BW
Full power bandwidth (−3 dB)
900
MHz
PGA (See Note 7)
PARAMETER
MIN
TYP
MAX
UNIT
Gain range (linear scale)
0.5
4
V/V
Gain step size (linear scale)
0.485
0.5
0.515
V/V
Gain error (deviation from ideal, all gain settings)
−3%
3%
Number of control bits
3
Bits
clamp amplifier and clamp DAC (See Note 8)
PARAMETER
MIN
TYP
MAX
UNIT
Resolution
10
Bits
DAC output range
REFB
REFT
V
DAC differential nonlinearity
−1
1
LSB
DAC integral nonlinearity
−3
3
LSB
Clamping analog output voltage range
0.1
AVDD−0.1
V
Clamping analog output voltage error
−40
40
mV
Clamping analog output bias voltage
MODE = AVDD AVDD/2 − 0.1
AVDD/2 + 0.1
mV
NOTES:
7. Gain settings increment by the gain step size for eight binary settings of 000 to 111 to correspond to the ideal gain range.
8. The CLAMPOUT pin must see a load capacitance of at least 10 nF to ensure stability of the on-chip clamp buffer. When using the
clamp for dc restoration, the signal coupling capacitor should be at least 10 nF. When using the clamp buffer as a dc biasing reference,
CLAMPOUT should be decoupled to analog ground through at least a 10-nF capacitor.



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