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WM8746 데이터시트(PDF) 12 Page - Wolfson Microelectronics plc

부품명 WM8746
상세설명  24BIT 192KHZ 6 CHANNEL DAC WITH VOLUME CONTROL
PDF  31 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8746 데이터시트(HTML) 12 Page - Wolfson Microelectronics plc

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WM8746
Advance Information
PP Rev 1.4 November 2001
12
DSP LATE MODE
In DSP late mode, the first bit is sampled on the BCKIN edge which detects a low to high transition
on LRCIN.
LRCIN
BCKIN
DIN0
Input Word Length (IWL)
1/fs
CHANNEL 0
LEFT
n
2
1
n-1
LSB
MSB
n
2
1
n-1
CHANNEL 0
RIGHT
2
1
CHANNEL 1
LEFT
n
n-1
CHANNEL 2
RIGHT
NO VALID DATA
1
Figure 8 DSP Late Mode Timing Diagram
In both early and late DSP modes, DAC0 left is always sent first, followed immediately by data words
for the other 5 channels. No BCKIN edges are allowed between the data words. The word order is
DAC0 left, DAC0 right, DAC1 left, DAC1 right, DAC2 left, DAC2 right.
SPLIT RATE MODE
The WM8746 can be used with differing sample rates on the front and rear channels. This allows
extremely high quality audio to be played on the front two channels whilst the other channels use
normal high quality data streams.
This mode will only work with a front data rate of 192kHz and a rear rate of 96kHz but can be used
with all the normal data formats except the two DSP modes and with the system at either 128fs or
192fs see Table 4.
When running in split rate mode all the channels are clocked in using a common BCKIN; the front
channels using LRCIN and all the other channels using LRCIN2 see Figure 9.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN0
2/fs
LSB
MSB
LSB
MSB
LEFT CHANNEL
RIGHT CHANNEL
n
2
1n
2
1n
2
1n
2
1
LSB
MSB
LSB
MSB
n
2
1
n
2
1
MSB
LSB
LSB
MSB
DIN1/2
LRCIN2
LEFT CHANNEL
RIGHT CHANNEL
Figure 9 Split Rate Audio Mode Timing Diagram
Notes:
1. Figure 9 shows the timing for left justified however this is similar for right justified and I
2S.
2. The edges of LRCIN and LRCIN2 must be coincidental.



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