WM8739 / WM8739L

Advanced Information

AI Rev 2.2 September 2001

17

LEFT CHANNEL

RIGHT CHANNEL

ADCLRC

BCLK

ADCDAT

1/fs

n

3

2

1

n-2

n-1

LSB

MSB

n

3

2

1

n-2

n-1

LSB

MSB

Figure 15 Right Justified Mode

DSP mode is where the left channel MSB is available on either the 1

(selectable by LRP) following a LRCLK transition high. Right channel data immediately follows left

channel data.

LEFT CHANNEL

RIGHT CHANNEL

ADCLRC

BCLK

ADCDAT

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

1 BCLK

Input Word Length (IWL)

Note: Input word length is defined by the IWL register, LRP = 1

1/fs

Figure 16 DSP Mode

The ADC digital audio interface modes are software configurable as indicated in Figure 16. Note that

dynamically changing the software format may results in erroneous operation of the interfaces and is

therefore not recommended.

The length of the digital audio data is programmable at 16/20/24 or 32 bits. Refer to the software

control table below. The data is signed 2’s complement. The ADC digital filters process data using 24

bits. If the ADC is programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data.

If the ADC is programmed to output 32 bits then it packs the LSBs with zeros.

ADCDAT is always an output. It powers up and returns from standby ‘low’.

ADCLRC and BCLK can be either outputs or inputs depending on whether the device is configured

as a master or slave. If the device is a master then the ADCLRC and BCLK signals are outputs that

default low. If the device is a slave then the ADCLRC and BCLK are inputs.