Rev. 3.05 May 27, 1999

2

©1999 National Semiconductor Corporation

Functional Description.

The CLC5902 block diagram is shown in Figure 2. The

CLC5902 contains two identical digital down-conversion

(DDC) circuits. Each DDC accepts a 14-bit sample at up

to 52MSPS, down converts from a selected carrier fre-

quency to baseband, decimates the signal rate by a pro-

grammable factor ranging from 32 to 16384, provides

channel filtering, and outputs quadrature symbols.

A crossbar switch enables either of the two inputs or a test

register to be routed to either DDC channel. Flexible chan-

nel filtering is provided by the two programmable deci-

mating FIR filters. The final filter outputs can be

converted to a 12-bit floating point format or standard

two’s complement format. The output data is available at

both serial and parallel ports.

The CLC5902 maintains over 100 dB of spurious free

dynamic range and over 100 dB of out-of-band rejection.

This allows considerable latitude in channel filter parti-

tioning between the analog and digital domains.

The frequencies, phase offsets, and phase dither of the two

sine/cosine numerically controlled oscillators (NCOs) can

be independently specified. Both channels share the same

decimation ratio, bandwidth, filter coefficients, and input/

output formats.

Each channel has its own AGC circuit for use with nar-

rowband radio channels where most of the channel filter-

ing precedes the ADC. The AGC closes the loop around

the CLC5526 DVGA, compressing the dynamic range of

the signal into the ADC. The AGC can be configured to

operate continuously or in a gated mode. The two AGC

circuits operate independently but share the same pro-

grammed parameters and control signals.

The chip receives configuration and control information

over a microprocessor-compatible bus consisting of an 8-

bit data I/O port, an 8-bit address port, a chip enable

strobe, a read strobe, and a write strobe. The chip’s control

registers (8 bits each) are memory mapped into the 8-bit

address space of the control port.

JTAG boundary scan and on-chip diagnostic circuits are

provided to simplify system debug and test.

The CLC5902 supports 3.3V I/O. The CLC5956 ADC

outputs are compatible with the CLC5902 inputs. The

CLC5902 outputs swing to the 3.3V rail so they can be

directly connected to 5V TTL inputs if desired.

Figure 2

CLC5902 Dual Digital Tuner/AGC Block Diagram with Control Register Associations

AIN

BIN

MUX

MUX

Channel A

Tuning,

Channel Filters, and

AGC (see Figure 14)

Channel B

Tuning,

Channel Filters, and

AGC (see Figure 14)

Input Source

Output Controls

Output Formatter

Floating Point:

32-bit Truncated or

24-bit Rounded or

16-bit Rounded or

8-bit Truncated

Two’s Complement:

4-bit Exponent and

8-bit Mantissa

or

AOUT/BOUT

BOUT

SCK

SFS

RDY

POUT[15..0]

PSEL[2..0]

POUT_EN

A_SOURCE

B_SOURCE

RATE

SOUT_EN

SCK_POL

SFS_POL

RDY_POL

MUX_MODE

PACKED

FORMAT

DEBUG_EN

DEBUG_TAP

CK

CLK

GEN

TEST_REG

Channel B Controls

GAIN_B

FREQ_B

PHASE_B

AGC_IC_B

AGC_RB_B

DITH_B

AGC_EN

Channel A Controls

GAIN_A

FREQ_A

PHASE_A

AGC_IC_A

AGC_RB_A

DITH_A

Common Channel Controls

DEC_BY_4

SCALE

EXP_INH

AGC_FORCE

AGC_RESET_EN

AGC_HOLD_IC

AGC_LOOP_GAIN

AGC_COUNT

AGC_TABLE

F1_COEFF

F2_COEFF

AGAIN[2..0]

ASTROBE

BGAIN[2..0]

BSTROBE

Microprocessor

Interface

RD

WR

CE

A[7:0]

D[7:0]

SI

MR

Sync

Logic

14

14

DEC

(see Figure 26)

A

B