CS5516-ASZ datasheet(26/41 Pages) CIRRUS

26 / 41 page

The filter will start a new convolution on the

next rising edge of the XIN clock after the 24th

SCLK falls.

Sleep Mode

The CS5516/20 configuration register has an

A/S bit which allows the users to put the device

in a sleep condition to lower quiescent power.

Upon reset the A/S bit device is set to a logic 0

which places the device in the ’awake’ condi-

tion. Writing a 1 to the A/S bit will shutdown

most of the chip, including the oscillator. It is

desirable to use the following sequence when

coming out of sleep. Write a logic 0 to the A/S

bit of the configuration register.

In the same

configuration word write a logic 1 to the RF bit

of the configuration register. Then wait until it is

certain that the oscillator has started. After the

oscillator has started or a clock present on the

XIN pin, set the RF bit back to 0. The user

should then wait at least 6 output word update

periods before expecting a valid output data

word.

Noise Performance

Typical noise performance for the converter is

listed in the specification tables for each PGA

gain. Figure 13 illustrates a noise histogram for

1000 output conversions from the CS5520. The

data for the histogram was collected using the

CDB5520 evaluation board; with VREF at 2.5

volts, PGA = 4, bipolar mode. The data shows

the standard deviation of the data set is 3.2

LSBs. One LSB is equivalent to [VREF X 2(bi-

polar)]/ [Inst amp gain X PGA gain X number

of codes] or (2.5 X 2)/ (25 X 4 X 2E20) = 47.7

nV. One standard deviation is equivalent to rms

if the data is Normal or Gaussian. The rms noise

presented by the plot is 153 nV, which is in

good agreement with the typical noise specifica-

tion of 150 nV for a PGA gain of 4.

Applications

See the Application Notes section of the databook.

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100

120

140

0 1 2 345 6 7 8

-1

-2

-3

-4

-5

-6

-7

-8

Figure 13. CS5520 Noise Histogram.

CS5516, CS5520

DS74F1

DS74F2

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