TLC532AI, TLC532AM, TLC533AI, TLC533AM

LinCMOS

™ 8-BIT ANALOG-TO-DIGITAL PERIPHERALS

WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS

SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986

POST OFFICE BOX 655303

3

functional description (continued)

A conversion cycle starts after a 2-byte instruction is written to the control register and the start conversion (SC)

bit is a logic high. This 2-byte instruction also selects the input analog channel to be converted. The status (EOC)

bit in the analog conversion data register is reset, and it remains reset until the conversion is complete, at which

time the status bit is set again. After conversion, the results are loaded into the analog conversion data register.

These results remain in the analog conversion data register until the next conversion cycle is complete. If a new

conversion command is entered into the control register while the conversion cycle is in progress, the on-going

conversion is aborted and a new channel acquisition cycle begins immediately.

The reset input R allows the device to be externally forced to a known state. When a low level is applied to the

R input for a minimum of three clock periods, the SC bit is cleared. The A/D converter is then idled and all the

outputs are placed in the high-impedance off-state. However, the content of the analog conversion data register

is not affected by the R input going to a low level.

Detailed information on interfacing to most popular microprocessors is readily available from the factory.

functional block diagram

Data Bus

Control Logic

Digital Data

Register

(Read Only)

8

12-Channel

Multiplexer

11

5

6

6

6

8

Analog MUX

Address

Control

Register

(Write Only)

8

Analog Conversion

Register

(Read Only)

8

8

8-Bit Analog-to-Digital

Converter

(Switched Capacitors)

Sample

and Hold

4

A1

(2 – 8 – 2 – 1)

R/W

CS

RS

R

CLOCK

REF +

REF –

Data Bus

Analog/Digital Input

(A10/D1 – A15/D6)

External Analog Input

(A0, A2 – A5)