A3

A1

C3

C1

B2

BYPASS

IN

EN

OUT

GND

4

BYPASS

5

OUT

EN

3

GND

2

IN

1

LP3985

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SNVS087AE – OCTOBER 2000 – REVISED MAY 2015

5 Pin Configuration and Functions

DBV Package

5 Pin SOT-23

Top View

YZR Package

5 Pin DSBGA

Top View

Pin Functions

PIN

TYPE

DESCRIPTION

DSBGA

SOT-23

NAME

NUMBER

BYPASS

A3

4

I/O

Optional bypass capacitor for noise reduction

EN

A1

3

I

Enable input logic, enable high

GND

B2

2

GND

Common ground

IN

C3

1

I

Input voltage of the LDO

OUT

C1

5

O

Output voltage of the LDO

(1)

The pin numbering scheme for the DSBGA package was revised in April 2002 to conform to JEDEC standard. Only the pin numbers

were revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering

scheme had VEN as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and BYPASS as pin 5.

Copyright © 2000–2015, Texas Instruments Incorporated

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