Philips Semiconductors

PCA8565

Real time clock/calender

Product data

Rev. 01 — 31 March 2003

13 of 26

9397 750 10695

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

clock pulse. A slave receiver which is addressed must generate an acknowledge after

the reception of each byte. Also a master receiver must generate an acknowledge

after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges must pull down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration). A master receiver must signal an end of data to the transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In

this event the transmitter must leave the data line HIGH to enable the master to

generate a stop condition.

9.5.1

Addressing

addressed first. The addressing is always carried out with the first byte transmitted

after the start procedure.

The PCA8565 acts as a slave receiver or slave transmitter. Therefore the clock signal

SCL is only an input signal, but the data signal SDA is a bidirectional line.

The PCA8565 slave address is shown in Figure 10.

Fig 9.

MBC602

S

START

condition

9

8

2

1

clock pulse for

acknowledgement

not acknowledge

acknowledge

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

Fig 10. Slave address.

MCE189

1

0

1

0

0

0

1

R/W

group 1

group 2