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HV528K6-G 데이터시트(PDF) 2 Page - Supertex, Inc |
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HV528K6-G 데이터시트(HTML) 2 Page - Supertex, Inc |
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2 / 8 page ![]() 2 HV528 ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Ordering Information Device Package Option 32-Lead QFN 5.00x5.00mm body 1.00mm height (max) 0.50mm pitch HV528 HV528K6-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value Logic supply, V DD -0.5V to 7.0V High voltage supply, V PP 215V Translator supply voltage, V BIAS -0.5V to 7.0V Logic input levels -0.5V to V DD +0.5V Operating junction temperature -40°C to +125°C Storage temperature range -65°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Pin Configuration Operating Supply Voltages and Conditions Sym Parameter Min Typ Max Units Conditions V DD Logic supply voltage 1.7 3.0 5.5 V --- V BIAS Level translator supply voltage 5.4 - 6.6 V --- V PP Positive high voltage supply 50 - 200 V --- V IH High-level input voltage 0.9V DD - V DD V --- V IL Low-level input voltage 0 - V --- T A Operating temperature 0 - +70 °C --- Notes: 1. External ground noise reduction circuit will be provided by design upon characterization. Power-up sequence should be the following*: 1. Apply ground 2. Apply V DD 3. Set all inputs (D IN, CLK, LE , POL) to a known state 4. Apply V BIAS 5. Apply V PP Power-down sequence should be the reverse of the above * This power up sequence requires an external high voltage diode between V DD and VPP. Without the diode, power up VPP to a VDD level first to bias the silicon substrate. After all other signals are powered, finish raising the V PP to its final level. 1 32 Product Marking HV528 LLLLLL YYWW AAACCC L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging 32-Lead QFN (K6) 32-Lead QFN (K6) (top view) (Bottom side exposed center pad is at V PP potential) |
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