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LP5523 데이터시트(PDF) 6 Page - Texas Instruments

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부품명 LP5523
상세설명  LP5523 Programmable 9-Output LED Driver
PDF  56 Pages
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LP5523 데이터시트(HTML) 6 Page - Texas Instruments

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LP5523
SNVS550D – SEPTEMBER 2009 – REVISED MAY 2013
www.ti.com
Logic Interface Characteristics
(1)(2)(3)
(continued)
Symbol
Parameter
Condition
Min
Typ
Max
Units
IL
Output Leakage Current
VOUT = 2.8V
1.0
µA
Recommended External Clock Source Conditions
(1) (2) (3) (4) (5)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Logic input CLK
fCLK
Clock Frequency
32.7
kHz
tCLKH
High Time
6
µs
tCLKL
Low Time
6
µs
tr
Clock Rise Time
10% to 90%
2
µs
tf
Clock Fall Time
90% to 10%
2
µs
(1)
The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured.
(2)
All voltages are with respect to the potential at the GND pin.
(3)
Min and Max limits are ensured by design, test, or statistical analysis.
(4)
Specification is ensured by design and is not tested in production. VEN = 1.65V to VDD.
(5)
The ideal external clock signal for the LP5523 is a 0V to VEN 25% to 75% duty-cycle square wave. At frequencies above 32.7 kHz,
program execution will be faster, and at frequencies below 32.7 kHz program execution will be slower.
Serial Bus Timing Parameters (SDA, SCL)
(1) (2) (3) (4)
Symbol
Parameter
Limit
Units
Min
Max
fSCL
Clock Frequency
400
kHz
1
Hold Time (repeated) START Condition
0.6
µs
2
Clock Low Time
1.3
µs
3
Clock High Time
600
ns
4
Setup Time for a Repeated START Condition
600
ns
5
Data Hold Time
50
ns
6
Data Setup Time
100
ns
7
Rise Time of SDA and SCL
20+0.1 Cb
300
ns
8
Fall Time of SDA and SCL
15+0.1 Cb
300
ns
9
Set-up Time for STOP condition
600
ns
10
Bus Free Time between a STOP and a START Condition
1.3
µs
Cb
Capacitive Load Parameter for Each Bus Line.
10
200
ns
Load of One Picofarad Corresponds to One Nanosecond.
(1)
The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured.
(2)
All voltages are with respect to the potential at the GND pin.
(3)
Min and Max limits are ensured by design, test, or statistical analysis.
(4)
Specification is ensured by design and is not tested in production. VEN = 1.65V to VDD.
6
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Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LP5523



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