ICS501B datasheet(3/6 Pages) ICST

3 / 6 page

LOCO™ PLL Clock Multiplier

MDS 501B C

Revision 120704

In te gr at ed Circuit Syst ems ● 525 Ra ce St reet , San Jose, CA 9512 6 ● t e l (4 08) 297 -1 201 ● www.icst.com

ICS501B

External Components

Decoupling Capacitor

As with any high-performance mixed-signal IC, the

ICS501B must be isolated from system power supply

noise to perform optimally.

A decoupling capacitor of 0.01µF must be connected

between VDD and the GND. It must be connected

close to the ICS501B to minimize lead inductance. No

external power supply filtering is required for the

ICS501B.

Series Termination Resistor

A 33

Ω terminating resistor can be used next to the CLK

pin for trace lengths over one inch.

Crystal Load Capacitors

The total on-chip capacitance is approximately 12 pF. A

parallel resonant, fundamental mode crystal should be

used. The device crystal connections should include

pads for small capacitors from X1 to ground and from

X2 to ground. These capacitors are used to adjust the

stray capacitance of the board to match the nominally

required crystal load capacitance. Because load

capacitance can only be increased in this trimming

process, it is important to keep stray capacitance to a

minimum by using very short PCB traces (and no vias)

between the crystal and device. Crystal capacitors, if

needed, must be connected from each of the pins X1

and X2 to ground.

The value (in pF) of these crystal caps should equal

(CL -12 pF)*2. In this equation, CL= crystal load

capacitance in pF. Example: For a crystal with a 16 pF

load capacitance, each crystal capacitor would be 8 pF

[(16-12) x 2] = 8.

ICS501B 데이터시트(PDF) 3 Page - Integrated Circuit Systems