LP8545 datasheet(36/44 Pages) TI1

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LP8545

SNVS635D – APRIL 2010 – REVISED DECEMBER 2013

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EEPROM ADDRESS 4 register

DRV_HEADR

2:0

R/W

LED output driver headroom control. VSAT is the saturation voltage of the driver,

typically 200 mV.

000 = VSAT + 125 mV

001 = VSAT + 250 mV

010 = VSAT + 375 mV

011 = VSAT + 500 mV

100 = VSAT + 625 mV

101 = VSAT + 750 mV

110 = VSAT + 875 mV

111 = VSAT + 1000 mV

EEPROM Address 5

Address A5h

EEPROM ADDRESS 5 register

EN_VSYNC

DITHER[1:0]

VBOOST[4:0]

Name

Bit

Access

Description

EN_VSYNC

R/W

Enable VSYNC function

0 = VSYNC input disabled

1 = VSYNC input enabled. VSYNC signal is used by the internal PLL to generate

PWM output and boost frequency.

DITHER

6:5

R/W

Dither function controls

00 = Dither function disabled

01 = 1-bit dither used for output PWM transitions

10 = 2-bit dither used for output PWM transitions

11 = 3-bit dither used for output PWM transitions

VBOOST

4:0

R/W

Boost voltage control from 10V to 40V with 1V step (without FB resistor divider). If

adaptive boost control is enabled, this sets the initial start voltage for the boost

converter. If adaptive mode is disabled, this will directly set the output voltage of

the boost converter.

0 0000 = 10V

0 0001 = 11V

0 0010 = 12V

...

1 1101 = 39V

1 1110 = 40V

1 1111 = 40V

EEPROM Address 6

Address A6h

EEPROM ADDRESS 6 register

PLL[12:5]

Name

Bit

Access

Description

PLL

7:0

R/W

13-bit counter value for PLL, 8 MSB bits. PLL[12:0] bits are used when en_vsync =

1. See table below for PLL value calculation.

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