Top View

Bottom View

B1

GND

OUT1

A2

IN

B2

OUT2

C2

A1

EN1

B1

GND

C1

EN2

OUT1

A2

C1

EN2

A1

EN1

IN

B2

OUT2

C2

3

LP8900

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SNVS542E – MAY 2008 – REVISED JUNE 2016

Product Folder Links: LP8900

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Copyright © 2008–2016, Texas Instruments Incorporated

5 Default Device Options

ORDERABLE NUMBER

OUT1

OUT2

LP8900TLE-3333

2.8 V

2.8 V

LP8900TLE-AAAH

2.7 V

2.7 V

LP8900TLE-AAEB

2.8 V

2.7 V

LP8900TLE-AAEC

2.8 V

1.2 V

6 Pin Configuration and Functions

YZR Package

6-Pin DSBGA

Pin Functions

PIN

TYPE

DESCRIPTION

NUMBER

NAME

A1

EN1

I

Enable input; enables the regulator when

≥ 1.2 V. Enable Input has an internal 3-MΩ

pulldown resistor to GND.

Disables the regulator when

≤ 0.4 V.

A2

OUT1

O

Voltage output. A low ESR ceramic capacitor must be connected from this pin to GND.

(See Application and Implementation.) Connect this output to the load circuit.

B1

GND

G

Common ground.

B2

IN

I

Voltage supply input. A 1-µF capacitor must be connected from this pin to GND.

C1

EN2

I

Enable input; enables the regulator when

≥ 1.2 V. Enable input has an internal 3-MΩ

pulldown resistor to GND.

Disables the regulator when

≤ 0.4 V.

C2

OUT2

O

Voltage output. A low ESR ceramic capacitor must be connected from this pin to GND.

(See Application and Implementation.) Connect this output to the load circuit.