TLK1201ARCP_16 datasheet(13/24 Pages) TI1

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5 pF

Ω

LVTTL OUTPUT SWITCHING CHARACTERISTICS

CLOCK

80%

50%

20%

2 V

0.8 V

DATA

1.4 V

TRANSMITTER TIMING REQUIREMENTS

TLK1201ARCP, TLK1201AIRCP

ETHERNET TRANSCEIVERS

SLLS580D – FEBRUARY 2004 – REVISED SEPTEMBER 2007

Figure 8. Transmitter Test Setup

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tr(RBC)

Clock rise time

0.3

1.5

tf(RBC)

Clock fall time

0.3

1.5

80% to 20% output voltage, C = 5 pF (see

Figure 9)

Data rise time

0.3

1.5

Data fall time

0.3

1.5

TBI normal mode, (see Figure 3), Rω = 125 MHz

2.5

Data setup time (RD0–RD9), Data

tsu(D1)

valid prior to RBC0 rising

TBI normal mode, (see Figure 3), Rω = 61.44 MHz

TBI normal mode, (see Figure 3), Rω = 125 MHz

Data hold time (RD0–RD9), Data valid

th(D1)

after RBC0 rising

TBI normal mode, (see Figure 3), Rω = 61.44 MHz

tsu(D2)

Data setup time (RD0–RD4)

DDR mode, Rω = 125 MHz, (see Figure 4)

th(D2)

Data hold time (RD0–RD4)

DDR mode, Rω = 125 MHz, (see Figure 4)

0.8

tsu(D3)

Data setup time (RD0–RD9)

TBI half-rate mode, Rω = 125 MHz, (see Figure 2)

2.5

th(D3)

Data hold time (RD0–RD9)

TBI half-rate mode, Rω = 125 MHz, (see Figure 2)

1.5

Figure 9. TTL Data I/O Valid Levels for AC Measurement

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tsu(D4)

Data setup time (TD0–TD9)

1.6

TBI modes

th(D4)

Data hold time (TD0–TD9)

0.8

tsu(D5)

Data setup time (TD0–TD9)

0.7

DDR modes

th(D5)

Data hold time (TD0–TD9)

0.5

tr, tf

TD[0,9] data rise and fall time

See Figure 9

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