MPC9448

MOTOROLA

TIMING SOLUTIONS

2

Figure 1. Logic Diagram

Figure 2. 32--Lead Package Pinout

(Top View)

1

0

CCLK

STOP

CLK

CLK_SEL

OE

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

PCLK

Q9

Q11

Q10

CLK_STOP

SYNC

PCLK

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

12

3

4

5

6

7

8

24

23 22 21

20 19

18 17

16

MPC9448

Q3

Q2

GND

Q1

Q0

GND

GND

Q8

Q9

GND

Q10

Q11

(all input resistors have a value of 25kΩ)

Table 1. FUNCTION TABLE

Control

Default

0

1

CLK_SEL

1

PECL differential input selected

CCLK input selected

OE

1

Outputs enabled

CLK_STOP

1

Outputs synchronously stopped in logic low state

Outputs active

1. OE=0 will high-impedance tristate all outputs independent on CLK_STOP.

Table 2. PIN CONFIGURATION

Pin

I/O

Type

Function

PCLK, PCLK

Input

LVPECL

Clock signal input

CCLK

Input

LVCMOS

Alternative clock signal input

CLK_SEL

Input

LVCMOS

Clock input select

CLK_STOP

Input

LVCMOS

Clock output enable/disable

OE

Input

LVCMOS

Output enable/disable (high--impedance tristate)

Q0--11

Output

LVCMOS

Clock outputs

GND

Supply

Ground

Negative power supply (GND)

Supply

the positive power supply for correct operation

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com