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MCP19116T-E/MJ 데이터시트(PDF) 73 Page - Microchip Technology

부품명 MCP19116T-E/MJ
상세설명  Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller with Improved 8k Word Core
PDF  246 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP19116T-E/MJ 데이터시트(HTML) 73 Page - Microchip Technology

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 2015-2016 Microchip Technology Inc.
DS20005479B-page 73
MCP19116/7
FIGURE 10-5:
ASYNCHRONOUS RECEPTION
FIGURE 10-6:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 10-7:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
START
bit
bit7/8
bit1
bit0
bit7/8
bit0
STOP
bit
START
bit
START
bit
bit7/8 STOP
bit
RX (pin)
Rcv Buffer Reg
Rcv Shift Reg &
Read Rcv
Buffer Reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
STOP
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
RCIDL
Start
bit
bit1
bit0
bit8
bit0
Stop
bit
Start
bit
bit8
Stop
bit
RX (pin)
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
WORD 1
RCREG
Note: This timing diagram shows a data byte followed by an address byte.The data byte is not read into the RCREG (receive buffer)
Bit8 = 0, Data Byte
Bit8 = 1, Address Byte
because ADDEN = 0.
RCIDL
Rcv Buffer Reg
Rcv Shift Reg &
Start
bit
bit1
bit0
bit8
bit0
Stop
bit
Start
bit
bit8
Stop
bit
RX (pin)
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
WORD 1
RCREG
Bit8 = 1, Address Byte
Bit8 = 0, Data Byte
Note: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG (receive buffer)
because ADDEN was not updated and still = 0.
RCIDL
Rcv Buffer Reg
Rcv Shift Reg &



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