TMS320VC549 datasheet(33/118 Pages) TI1

33 / 118 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

software-programmable PLL (’545A, ’546A, ’548, and ’549) (continued)

Bits 15 –12

PLLMUL. PLL multiplier. Defines the frequency multiplier in conjunction with PLLDIV and

PLLNDIV, as shown in Table 5.

Bit 11

PLLDIV. PLL divider. Defines the frequency multiplier in conjunction with PLLMUL and PLLNDIV,

as shown in Table 5.

0 = an integer multiply factor is used.

1 = a non-integer multiply factor is used.

Bits 10 –3

PLLCOUNT. PLL counter value. Specifies the number of input clock cycles (in increments of

16 cycles) for the PLL lock timer to count before the PLL begins clocking the processor after the

PLL is started. The PLL counter is a down-counter, which is driven by the input clock divided

by 16; therefore, for every 16 input clocks, the PLL counter decrements by one.

The PLL counter can be used to ensure that the processor is not clocked until the PLL is locked,

so that only valid clock signals are sent to the device.

Bit 2

PLLON/OFF. PLL on/off. Enables or disables the PLL part of the clock generator in conjunction

with the PLLNDIV bit. Note that PLLON/OFF and PLLNDIV can both force the PLL to run; when

PLLON/OFF is high, the PLL runs independently of the state of PLLNDIV.

PLLON/OFF

PLLNDIV

PLL STATE

Off

Bit 1

PLLNDIV. PLL clock generator select. Determines whether the clock generator works in PLL

mode or in divider (DIV) mode, thereby defining the frequency multiplier in conjunction with

PLLMUL and PLLDIV.

0 = Divider mode is used

1 = PLL mode is used

Bit 0

PLLSTATUS. PLL status. Indicates the mode in which the clock generator is operating.

0 = DIV mode

1 = PLL mode

Table 5. PLL Multiplier Ratio as a Function of PLLNDIV, PLLDIV, and PLLMUL

PLLNDIV

PLLDIV

PLLMUL

MULTIPLIER†

0–14

0.5

0.25

0–14

PLLMUL + 1

Reserved

0 or even

(PLLMUL + 1)

B 2

odd

PLLMUL

B 4

† CLKOUT = CLKIN x multiplier

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