MCP2035-ISLASHST datasheet(48/68 Pages) MICROCHIP

48 / 68 page

MCP2035

DS22304A-page 48

 2012 Microchip Technology Inc.

FIGURE 5-12:

Detailed SPI Timing (AFE).

5.30.2.1

Clamp On Command

This command results in activating (turning on) the

modulation transistor of the input channel.

5.30.2.2

Clamp Off Command

This command results in deactivating (turning off) the

modulation transistor of input channel.

5.30.2.3

Sleep Command

This command places the device in Sleep mode –

minimizing current draw by disabling all but the

essential circuitry. Any other command wakes the

device from Sleep (e.g., Clamp Off command).

5.30.2.4

Soft Reset Command

The device issues a Soft Reset when it receives an

external Soft Reset command. The external Soft Reset

command is typically used to end a SPI communication

sequence or to initialize the device for the next signal

detection sequence, etc. See Section 5.19 “Soft

Reset”

for more details on Soft Reset.

If a Soft Reset command is sent during a “Clamp-on”

condition, the device still keeps the “Clamp-on” condi-

tion after the Soft Reset execution. The Soft Reset is

executed in Active mode only, not in Standby mode.

The SPI Soft Reset command is ignored if the device is

not in Active mode.

5.30.2.5

AGC Preserve On Command

This command results in preserving the AGC level

during each AGC initialization time and applies the

value to the data slicing circuit for the following data

stream. The preserved AGC value is reset by a Soft

Reset, and a new AGC value is acquired and pre-

served when it starts a new AGC initialization time. This

feature is disabled by an AGC Preserve Off command

(see Section 5.18 “AGC Preserve”).

5.30.2.6

AGC Preserve Off Command

This command disables the AGC preserve feature and

returns to the normal AGC tracking mode, fast tracking

during AGC settling time and slow tracking after that

(see Section 5.18 “AGC Preserve”).

5.30.3

READ/WRITE COMMANDS FOR

CONFIGURATION REGISTERS

The device includes eight Configuration registers,

including a Column Parity register and STATUS regis-

ter. All registers are readable and writable via SPI com-

mands, except the STATUS register, which is read-

only. Bit 0 of each register is a row parity bit (except for

STATUS Register 7) that makes the register contents

an odd number (“1”) including the parity bit itself.

SCLK

SDIO

Command

Data Byte

Address

Row

Parity Bit

MSb

LSb

Note:

If the odd parity bits for the row and

column are incorrectly programmed, the

Parity Error Indicator (PEI) bit in the Status

output pin will pull low, which causes extra

current draws.

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