MPC508A, MPC509A

5

SBFS019A

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Differential Multiplexer Static Accuracy

Static accuracy errors in a differential multiplexer are diffi-

cult to control, especially when it is used for multiplexing

low-level signals with full-scale ranges of 10mV to 100mV.

The matching properties of the multiplexer, source and

output load play a very important part in determining the

transfer accuracy of the multiplexer. The source impedance

unbalance, common-mode impedance, load bias current mis-

match, load differential impedance mismatch, and common-

mode impedance of the load all contribute errors to the

multiplexer. The multiplexer ON resistance mismatch, leak-

age current mismatch and ON resistance also contribute to

differential errors.

The effects of these errors can be minimized by following the

general guidelines described in this section, especially for

low-level multiplexing applications. Refer to Figure 2.

Load (Output Device) Characteristics

•

Use devices with very low bias current. Generally, FET

input amplifiers should be used for low-level signals less

than 50mV FSR. Low bias current bipolar input amplifi-

ers are acceptable for signal ranges higher than 50mV

FSR. Bias current matching will determine the input

offset.

•

The system dc common-mode rejection (CMR) can never

be better than the combined CMR of the multiplexer and

driven load. System CMR will be less than the device

which has the lower CMR figure.

•

Load impedances, differential and common-mode, should

Ω or higher.

DISCUSSION OF

PERFORMANCE

DC CHARACTERISTICS

The static or dc transfer accuracy of transmitting the multi-

plexer input voltage to the output depends on the channel ON

resistance (R

the load bias current and the multiplexer leakage current.

Single-Ended Multiplexer Static Accuracy

The major contributors to static transfer accuracy for single-

ended multiplexers are:

Source resistance loading error;

Multiplexer ON resistance error;

and, dc offset error caused by both load bias current and

multiplexer leakage current.

Resistive Loading Errors

The source and load impedances will determine the input

resistive loading errors. To minimize these errors:

•

Keep loading impedance as high as possible. This mini-

mizes the resistive loading effects of the source resis-

tance and multiplexer ON resistance. As a guideline, load

Ω, or greater, will keep resistive load-

ing errors to 0.002% or less for 1000

Ω source imped-

Ω load impedance will increase source

loading error to 0.2% or more.

•

Use sources with impedances as low as possible. 1000

Ω

source resistance will present less than 0.001% loading

error and 10k

Ω source resistance will increase source

Input resistive loading errors are determined by the follow-

ing relationship (see Figure 1).

Source and Multiplexer Resistive Loading Error

∈+

=

+

++

×

()

%

RR

RR

RR

R

SON

SON

SON

L

100

where R

R

R

Input Offset Voltage

Bias current generates an input OFFSET voltage as a result

of the IR drop across the multiplexer ON resistance and

source resistance. A load bias current of 10nA will generate

an offset voltage of 20

µV if a 1kΩ source is used. In general,

for the MPC508A, the OFFSET voltage at the output is

determined by:

V

where I

I

R

R

Z

L

R

S4A

R

S48

R

OFF4A

R

OFF4B

C

CM

R

S1

R

S1B

R

ON1A

R

ON1B

I

L

Cd/2

Cd/2

R

CM

Rd/2

Rd/2

I

BIAS A

I

BIAS B

R

CM4

R

CM1

V

S1

V

S8

I

LB

FIGURE 2. MPC509A DC Accuracy Equivalent Circuit.

R

S1

R

S8

R

ON

R

OFF

V

S1

V

S8

Z

L

Measured

Voltage

I

L

V

M

I

BIAS

FIGURE 1. MPC508A DC Accuracy Equivalent Circuit.