EMC2113 datasheet(50/88 Pages) MICROCHIP

50 / 88 page

RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown

Datasheet

DS20005251A-page 50

 2013 Microchip Technology Inc.

7.10

Critical Temperature Limit Registers

The Critical Temperature Limit Registers store the Critical Temperature Limit. At power up, none of the

respective channels are linked to the SYS_SHDN pin or the Hardware set Thermal/Critical Shutdown

circuitry.

Whenever one of the registers is updated, two things occur. First, the register is locked so that it cannot

be updated again without a power on reset. Second, the respective temperature channel is linked to

the SYS_SHDN pin and the Hardware set Thermal/Critical Shutdown Circuitry. At this point, if the

measured temperature channel meets or exceeds the critical limit, the SYS_SHDN pin will be asserted,

the appropriate bit set in the Tcrit Status Register, and the TCRIT bit in the Interrupt Status Register

will be set.

7.11

Configuration Register

The Configuration Register controls the basic functionality of the EMC2113. The bits are described

below.

Bit 7 - MASK - Blocks the ALERT pin from being asserted.



‘0’ (default) - The ALERT pin is unmasked. If any bit in either status register is set, the ALERT pin

will be asserted (unless individually masked via the Mask Register)



‘1’ - The ALERT pin is masked and will not be asserted.

Bit 6 - WD_EN - Enables the Watchdog timer to operate in Continuous Mode.



‘0’ (default) - The Watchdog timer does not operate continuously. It will function upon power up and

at no other time.



‘1’ - The Watchdog timer operates continuously as described in Section 6.10.2, "Continuous

Operation".

Bit 3 - SYS3 - Enables the high temperature limit for the External Diode 3 channel to trigger the

Critical/Thermal Shutdown circuitry (see Section 6.1, "Critical/Thermal Shutdown").



‘0’ (default) - the External Diode 3 channel high limit will not be linked to the SYS_SHDN pin. If the

temperature meets or exceeds the limit, the ALERT pin will be asserted normally.

Table 7.15 Limit Registers

ADDR

R/W

DEFAULT

19h

R/W

once

External Diode

1 Tcrit Limit

Sign

64h

(+100°C)

1Ah

R/W

once

External Diode

2 Tcrit Limit

Sign

64h

(+100°C)

1Bh

R/W

once

External Diode

3 Tcrit Limit

Sign

64h

(+100°C)

1Dh

R/W

once

Internal Diode

Tcrit Limit

Sign

64h

(+100°C)

Table 7.16 Configuration Register

ADDR

R/W

DEFAULT

20h

R/W

Configuration

MASK

WD_EN

SYS3

SYS2

SYS1

APD

00h

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