TNETE2004PBE datasheet(2/47 Pages) TI1

부품명	TNETE2004PBE

상세설명	MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

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TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

description (continued)

PHY Status and Control Signals

PHY Data I/O

IEEE 1149.1

Std

Test-Access

Port

LED Drivers

MDIO and

TNETE2004 Control

Logic

PHY 3

PHY 2

PHY 1

PHY 0

To/From

10BASE-T

Network

TNETE2004 Control Signals

Manufacturing Test Data

To LED

Status

Indicators

Figure 1. TNETE2004 Architecture

The TNETE2004 provides PHY-interface functions for up to four 10BASE-T half- or full-duplex ports as shown

in Figure 1. The TNETE2004 contains four independent 10BASE-T transceivers in a single chip. Each

transceiver is compliant with IEEE Std 802.3, Section 14, and a compliant management serial-interface port

provides information for network management.

A typical application with external components is shown in Figure 2.

TNETE2004PBE 데이터시트(PDF) 2 Page - Texas Instruments