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TNETX3150AGGP 데이터시트(PDF) 96 Page - Texas Instruments

부품명 TNETX3150AGGP
상세설명  ThunderSWITCHE 15-PORT 10-/100-MBIT/S ETHERNETE SWITCH
PDF  113 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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TNETX3150AGGP 데이터시트(HTML) 96 Page - Texas Instruments

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TNETX3150/TNETX3150A
ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH
SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997
96
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
DIO write cycle
D TNETX3150/TNETX3150A host-register address data SAD1–SAD0 and SDATA7–SDATA0 are asserted
and SRNW is taken low.
D After the setup time, SCS is taken low, initiating a write cycle.
D The TNETX3150/TNETX3150A pulls SRDY low as the data is accepted and SDATA7–SDATA0,
SAD1–SAD0, and SRNW are deasserted after the hold time is satisfied.
D SCS is taken high by the host to complete the cycle, causing SRDY to be deasserted and SRDY is driven
high for one cycle before being placed in the high-impedance (Z) state.
timing requirements over recommended operating conditions (see Note 11 and Figure 39)
write cycle DIO interface
NO
TNETX3150
TNETX3150A
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
1
tw(SCS)
Pulse duration, SCS low
40
40
ns
2
tsu(SAD)
Setup time, SAD1–SAD0 valid before SCS
↓
0
0
ns
3
tsu(SDATA)
Setup time, SDATA7–SDATA0 valid before SCS
↓
0
0
ns
4
tsu(SRNW)
Setup time, SRNW low before SCS
↓
0
0
ns
NOTE 11: The DIO interface/DIO write cycle is asynchronous, allowing easy adaptation to a range of microprocessor devices and computer
system interfaces.
operating characteristics over recommended operating conditions (see Note 11 and Figure 39)
write cycle DIO interface
NO
PARAMETER
TNETX3150
TNETX3150A
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
5
tw(SRDY)
Pulse duration, SRDY high
20
20
ns
6
td(SRNW)
Delay time, from SRDY
↓ to SRNW↑
0
0
ns
7
td(SAD)
Delay time, from SRDY
↓ to SAD1–SAD0 invalid
0
0
ns
8
td(SDATA)
Delay time, from SRDY
↓ to SDATA7–SDATA0 invalid
0
0
ns
9
td(SCS-SRDY)1
Delay time from SCS
↑ to SRDY↑
0
20
0
60
ns
10
td(SCS-SRDY)2
Delay time from SCS
↓ to SRDY↓
0
0
ns
NOTE 11: The DIO interface/DIO write cycle is asynchronous, allowing easy adaptation to a range of microprocessor devices and computer
system interfaces.



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