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TNETX3150GGP 데이터시트(PDF) 104 Page - Texas Instruments

부품명 TNETX3150GGP
상세설명  ThunderSWITCHE 15-PORT 10-/100-MBIT/S ETHERNETE SWITCH
PDF  113 Pages
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TNETX3150GGP 데이터시트(HTML) 104 Page - Texas Instruments

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TNETX3150/TNETX3150A
ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH
SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997
104
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
operating characteristics over recommended operating conditions (see Figure 45)
MII transmit 100/200 Mbit/s (XX = ports 00–02)
NO
PARAMETER
TNETX3150
TNETX3150A
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1
td(MXXTXD)1
Delay time, from MXXTCLK
↑ to MXXTXD3–MXXTXD0 valid
5
25
2.5
25
ns
1†
td(MXXTXD)2
Delay time, from MXXTCLK
↑ to MXXTXD7–MXXTXD0 valid
5
25
2.5
25
ns
1
td(MXXTXEN)
Delay time, from MXXTCLK
↑ to MXXTXEN valid
5
25
2.5
25
ns
1
td(MXXTXER)
Delay time, from MXXTCLK
↑ to MXXTXER valid
5
25
2.5
25
ns
† Also applies to the uplink (port 00) when operating in the 200 Mbit/s mode, except that MXXRXD3–MXXRXD0 is replaced with
MXXRXD7–MXXRXD0 and MXXRXDVX is used.
MXXTXD3–MXXTXD0 is driven by the reconciliation sublayer synchronous to the MXXTCLK. MXXTXEN is
asserted and deasserted by the reconciliation sublayer synchronous to the MXXTCLK rising edge. MXXTXER
is driven synchronous to the rising edge of MXXTCLK (XX = ports 00–02).
MXXTCLK
(input)
MXXTXD7–MXXTXD0
MXXTXD3–MXXTXD0
MXXTXEN
MXXTXER (outputs)
1
Figure 45. Ports (00–02) Transmit Interface Timing



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